1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a dual port static random access memory (SRAM) device having a memory cell comprised of a plurality of transistors.
2. Description of the Related Art
Semiconductor memory devices are classified into dynamic random access memories (DRAMs) and static random access memories (SRAMs). SRAMs advantages include high operation speed, low power consumption, and simple operation. In addition, there is no need to refresh data stored in SRAMs. Since SRAMs are compatible with a logic semiconductor device manufacturing process, they are generally used as embedded memories.
A typical SRAM cell includes two driver transistors (or pull-down transistors), two load devices, and two pass transistors (or access transistors). According to the type of a load device an SRAM includes, SRAM is classified into CMOS, high load resistor (HLR), or thin film transistor (TFT) types. A CMOS-type SRAM adopts a P channel-type MOS (PMOS) transistor as a load device, an HLR-type SRAM adopts a high resistor as a load device, and a TFT-type SRAM adopts a polysilicon TFT as a load device.
Therefore, a CMOS-type SRAM memory cell typically consists of 6 transistors, including two PMOS transistors used as load devices. Of the 6 transistors, four are generally N channel-type MOS (NMOS) transistors. Of the four NMOS transistors, two form inverters with the two PMOS transistors, and two are pass transistors.
FIG. 1 is a circuit diagram of an equivalent circuit of a single port SRAM device including 6 transistors. The memory cell layout of the single port SRAM device is disclosed in Japanese Patent Publication No. 10-178110.
Referring to FIG. 1, a first PMOS transistor P1 and a first NMOS transistor N1 constitute a first CMOS inverter, a second PMOS transistor P2 and a second NMOS transistor N2 constitute a second CMOS inverter. An input port of the first CMOS inverter and an output port of the second CMOS inverter are connected at memory node M1, and an output port of the first CMOS inverter and an input port of the second CMOS inverter are connected at a second memory node M2. This structure enables the first and second CMOS inverters to constitute a flip-flop circuit.
NMOS transistors N3 and N4 are pass transistors and also serve as access transistors. The gate of each of the pass transistors N3 and N4 is connected to a wordline (WL). The source and drain of the transistor N3 are connected to the first memory node M1 and a bitline BL, respectively, and the source and drain of the transistor N4 are connected to the second memory node M2 and a complementary bitline /BL, respectively.
At the memory cell level, numerous factors affect operation speed in a CMOS SRAM device, i.e., the resistance characteristics of interconnections and the amount of parasitic capacitance occurring between a bitline and a complementary bitline adjacent to the bitline.
The number of data read or write ports, also affects operation speed of SRAM devices. For example, in single port SRAM device, a pair of bitlines, connected to each other through a pass transistor, serves as an input port and an output port. When the single port SRAM device inputs or outputs data using the pair of bitlines, other data cannot be input or output via the pair of bitlines, data is not processed in parallel. For these reasons, operation speed of single port SRAM devices is limited.
A variety of multi-port CMOS SRAM devices, including a plurality of input and/or output ports, have been suggested. U.S. Pat. Nos. 5,754,468 and 6,005,795 disclose the memory cell layout of an equivalent circuit of a multi-port SRAM device.
A multi-port SRAM device can simultaneously carry out various operations, such as inputting, outputting, writing, and reading data, using different ports provided to serve different operations. In addition, the multi-port SRAM device can output data stored in a single memory cell to another system via each port. Therefore, the multi-port SRAM device is convenient for high-speed operations and data parallel processing systems.